Synthesis Timing Constraints

Topics covered –

  1. How to constrain the input, output and internal path of a single clock design
    • What are the different Timing paths
    • How to model clock skew and clock transition time
    • How to constrain different timing paths
    • Concept of virtual clock
    • Concept of time budgeting
  2. How to constrain the input and output of a single clock design in different scenarios
    • Input delay: Falling clock edge
    • Input delay: Multiple input paths
    • Output delay: Falling clock edge
    • Output delay: Multiple output paths
  3. How to constrain multiple synchronous clock design
    • How to apply multiple delay constraint on the same port
    • Concept of base period
  4. How to constrain asynchronous clocks and generated clocks in a design
    • How to constrain generated clocks
    • How to constrain asynchronous clocks
  5. How to constrain logically exclusive clocks in a design
    • Four different scenarios explained
  6. How to constrain multi-cycle path in a design
    • A multi-cycle path implemented in a design
    • How to constrain a multi-cycle path for setup timing
    • How to constrain a multi-cycle path for hold timing