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- Basics –
- Setup and Hold time (coming soon)
- Recovery and Removal time (coming soon)
- Time borrowing in Latches (coming soon)
- Synthesis Timing constraints –
- How to constrain the input, output and internal path of a single clock design
- How to constrain the input and output of a single clock design in different scenarios
- How to constrain multiple synchronous clock design
- How to constrain asynchronous clocks and generated clocks in a design
- How to constrain logically exclusive clocks in a design
- How to constrain multi-cycle path in a design
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