JTAG Architecture

JTAG is the acronym for Joint Test Action Group, a name for the group of people that developed the IEEE 1149.1 standard.
The functionality usually offered by JTAG is Debug Access (through User Data Registers) and Boundary Scan (through Boundary Scan Registers) –

  •  Debug Access is used by debugger tools to access the internals of a chip (like registers, some control bits), while making its functionality available and modifiable.
  •  Boundary Scan is used to implement hierarchical scan in larger subsystems, control primary inputs and observe primary outputs for scan test coverage improvement.

Broadly JTAG architecture comprises of four major components –

  1.  Test Access Port (TAP)
  2.  TAP Controller
  3.  Registers
      3.1.  Instruction Register
      3.2.  Data Registers
             3.2.1.  Bypass Register
             3.2.2.  Boundary Scan Register
             3.2.3.  Device ID Register (optional)
             3.2.4.  User Data Registers (optional)
  4.  Instruction Decoder

Figure 1: A top level view of JTAG Architecture