In modern day chips, sometimes it is necessary to switch between two different clocks when the chip is running. What will happen if we use the normal mux to switch clocks? Well if you see the waveform in Figure 2, everything is fine but if you see the waveform in Figure 3, there are glitches. Why is it so? It is because, in Figure 2, the ‘select’ signal changes its value when ‘both’ the clocks are low, but in Figure 3 it is not the case.
This kind of glitch may lead to unwanted behavior in the circuit. One way to avoid it is to gate both the clocks just before changing the ‘select’, so that when switching occurs both the clocks are low. However there is a better option available in terms of using Glitch free clock mux or commonly called clock mux. One method of implementing a glitch free clock mux in shown below [Note: The flops have active low reset but it is not shown in the diagram to avoid congestion]. As shown in the Figure 5, there is no glitch when the ‘select’ changes.
Although the above implementation of glitch free clock mux solves our purpose, but there is a catch. The ‘select’ pin could be asynchronous to clk1 and clk2, and if it changes its value very near to the capturing edge of the flop this may lead to metastability. So it is better to use a double synchronizer instead of a single flop in a glitch free clock mux, as shown in Figure 6 [Note: The double synchronizers have active low reset but it is not shown in the diagram to avoid congestion].
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