Constraining timing paths in Synthesis – Part 2

This is article-2 of how to define Synthesis timing constraint

Input Delay: Falling Clock Edge

Let’s review the set_input_delay command which was covered here. When we use –

set_input_delay -max 1.5 -clock CLK [get_ports Input1]

the synthesis tool assumes the data is launched by a positive edge triggered flop from the external logic (and the maximum input delay for the setup analysis is 1.5ns).

But if the data is launched by a negative edge triggered flop, then we must modify the constraint so that the synthesis tool becomes aware of it. Basically, we have to include a clock_fall option with the constraint.

Figure 1

Consider the example shown in Figure 1; it is given that the clock-to-Q delay of FF-3 is 0.2ns and the maximum delay associated with combo logic-4 is 0.8ns. As shown in the diagram, the FF-3 is a negative edge triggered flip-flop. Therefore, to constrain the input port, we have to use –

create_clock -period 5 [get_ports CLK]
set_input_delay -max 1 -clock CLK -clock_fall [get_ports Input1]

Input Delay: Multiple Input Paths

Figure 2

Consider the example shown in Figure 2; there are two paths that are being multiplexed and connected to our IP’s input port – Input1. The top path is launched by a negative edge of clock and the bottom path by a positive edge of same clock. We would like the synthesis tool to consider the arrival time of both paths and to constrain our input combo logic-1 for the latest arrival of the two paths.

Assume – the clock period is 10ns, the clock-to-Q delay of both FF-3 and FF-4 is 0.2ns; the delays associated with combo logic-4 and combo logic-5 are 0.8ns and 2.3ns respectively; the delay due to mux is 0.5ns.

To do this, we start by creating the clock –

create_clock -period 10 [get_ports CLK]

Then we define the arrival time of top path –

set_input_delay -max 1.5 -clock CLK -clock_fall [get_ports Input1]

And finally, we constrain the other path (here we need a add_delay option since we are applying the constraint on the same port that is already constrained; this ensures the second constraint doesn’t overwrite the first one) –

set_input_delay -max 3 -clock CLK -add_delay [get_ports Input1]

After constraining both the paths, the synthesis tool analyzes both the paths and optimizes the input path of our design with the more restrictive of the two (i.e. considering the worst-case scenario).

Now let’s calculate the maximum delay for combo logic-1 assuming the FF-1 has a 0.5ns setup requirement. As shown in the timing diagram below – the maximum delay is 3ns (i.e. (10ns – 0.5ns) – 6.5ns).

Output Delay: Falling Clock Edge

We also discussed about the set_output_delay command here. When we use –

set_output_delay -max 2 -clock CLK [get_ports Output1]

the synthesis tool assumes the data is captured by a positive edge triggered flop in the external logic (and the maximum output delay for the setup analysis is 2ns).

But if the data is captured by a negative edge triggered flop, then we must modify the constraint so that the synthesis tool becomes aware of it. Here also we have to include a clock_fall option with the constraint.

Figure 3

Consider the example shown in Figure 3; it is given that the setup time of FF-3 is 0.4ns and the maximum delay associated with combo logic-4 is 1.6ns. As shown in the diagram, the FF-3 is a negative edge triggered flip-flop. Therefore, to constrain the output port, we have to use –

create_clock -period 5 [get_ports CLK]
set_output_delay -max 2 -clock CLK -clock_fall [get_ports Output1]

Output Delay: Multiple Output Paths

Figure 4

Consider a case as shown is Figure 4; IP-2 has two capturing paths, the top path is being captured by a negative edge triggered flip-flop, while the bottom path is captured by a positive edge triggered flip-flop. We would like to apply constraints to the output port – Output1, so that the synthesis tool will consider both the paths while optimizing our IP’s output path to Output1.

Assume – the clock period is 10ns, the setup time of both FF-3 and FF-4 is 0.4ns; the delays associated with combo logic-4 and combo logic-5 are 1.1ns and 7.6ns respectively.

To do this, we start by creating the clock –

create_clock -period 10 [get_ports CLK]

Then we define the arrival time of one path (the bottom path) –

set_output_delay -max 8 -clock CLK [get_ports Output1]

And finally, we constrain the other path (here we need a add_delay option since we are applying the constraint on the same port that is already constrained; this ensures the second constraint doesn’t overwrite the first one) –

set_output_delay -max 1.5 -clock CLK -clock_fall -add_delay [get_ports Output1]

Now let’s calculate the maximum delay allowed for combo logic-3 assuming the FF-2 has a 0.5ns clock-to-Q delay. As shown in the timing diagram below – the maximum delay is 1.5ns.