Now that we are familiar with the JTAG architecture, let us take an example to understand how TAP can be used for some debug access. Suppose there is a 3-bit control signal in a design that we want to have the access to modify for some debug purpose. Assume that during normal functional operation the control signal should be 3’b111; but for some debug purpose we want to change it to, say 3’b100. Let’s see how we can do that using Test Access Ports.
Assume we have a 4-bit Instruction Register (IR) in our JTAG. First we have to create a 3-bit User Data Register (User DR) in our JTAG and connect it to the control signal that we want to modify. Then we have to assign an opcode to the User DR, say 1010 (4-bit opcode as we have a 4-bit IR). While creating the User DR, we have to ensure that the reset value of the register is 3’b111 (Why? Because as mentioned above during normal functional operation the control signal should be 3’b111). The User DR drives 3’b111 to the control signal until we update the DR with another value; typically in a chip power on process the JTAG comes out of reset first before any other logic, so the control signal inside our logic will get its required value of 3’b111 before the functional logic comes out of reset.
The timing diagram in Figure 1 shows how to update the User Data Register with value 3’b100. This timing diagram is from an industry standard JTAG where the TMS, TDI and Hold Register of DR and IR changes value at the nededge of the clock, whereas the FSM and Shift Register of DR and IR works at the posedge of the clock.
We started from the Test-Logic Reset state of the 16 state FSM discussed here and reached the Shift IR state by setting the TMS to the required value. Then through the TDI, we shifted-in the opcode (4’b1010) of the User Data Register into the Instruction Register. Initially the shift register and hold register of the IR was zero, which is its reset value; 4’b1010 was shifted in serially from LSB to MSB. Once the required opcode was loaded into the shift register of IR, we moved to the Update IR state by changing the TMS value. In the Update IR state the hold register of IR was updated with the value present in its shift register. Then the Instruction Decoder decoded this value and established a path between TDI and the User Data Register. Then we exited the Update IR state and moved to the Shift DR state, where we serially loaded our required value of 3’b100 into the shift register of User DR from LSB to MSB. Once 3’b100 was loaded into the shift register, we moved to the Update DR state. In Update DR state the hold register of DR is updated with 3’b100 and at this point only the control signal value changed from 3’b111 to 3’b100.
VLSI Tutorials 