Constraining Multiple Synchronous Clock Design in Synthesis

This is article-3 of how to define Synthesis timing constraint

Consider the example shown in Figure 1, where we have multiple clocks. As shown in Figure 2, the PLL is generating a main clock named CLKA of frequency 3 GHz, and there are 4 dividers generating CLKB, CLKC, CLKD and CLKE of frequency 333.3 MHz, 500 MHz, 750 MHz and 1 GHz respectively, from the main clock. Since all these clocks are derived from the same clock source, they are all synchronous to each other. Now coming back to the Figure 1, notice that some clocks don’t have a corresponding clock port on our IP. The clock to our IP is CLKC, but the input is launched from CLKB in IP-2 and the output is captured by different clocks – CLKD and CLKE in IP-3.

Figure 1: Multiple synchronous clocks in a design
Figure 2: Multiple synchronous clock generated from a PLL

Constraining the input port

Assume that the clock-to-Q delay of FF-3 is 0.05ns, the delay due to combo logic-4 is 0.5ns and the setup time of FF-1 is 0.1ns.

The clock that is driving the launching flop is CLKB whereas the clock for our IP is CLKC. We first create the clock for our IP with a period of 2ns (corresponding to CLKC’s frequency of 500 MHz) and apply that on our input port CLKC –

create_clock -period 2 [get_ports CLKC]

We then create a virtual clock of 3ns (corresponding to CLKB’s frequency of 333.3 MHz) which can be used as a reference clock for the input delay and name the virtual clock CLKB –

create_clock -period 3 -name CLKB

Now we simply specify the input delay relative to the virtual clock CLKB and we apply that to our input port Input1 –

set_input_delay -max 0.55 -clock CLKB [get_ports Input1]

Now let’s see how the synthesis tool determines the internal delay (in combo logic-1) for setup check.

The first thing the tool does when faced with a timing path that has multiple clocks is to derive the base period. The base period is defined as the least common multiple of the clock periods involved. For a clock period of 2ns and 3ns, the least common multiple is 6ns. The significance of the base period is it represents the smallest amount of time with unique clock waveform relationship. As shown in Figure 3, both the clocks launch at 0ns and then line up and starts rising again at 6ns. Basically the clocks waveform between 0-6ns will look the same as between 6-12ns, 12-18ns and so on; this means the tool only needs to find the worst case timing situation between 0-6ns and that will define the worst case timing for all the clock cycles.

Figure 3: Worst effective clock period for input path in the base period

Since there are multiple launching and capturing clock edges between 0-6ns, here is how the tool figures out the worst-case scenario – In our example CLKB is the launching clock, so the first launching edge happens at 0ns and the first capturing edge from CLKC happens at 2ns, so the first effective clock period is 2ns. The next possible launch edge of CLKB happens at 3ns and the next capturing CLKC edge happens after that at 4ns, so this effective clock period is 1ns, which is smaller than 2ns. Since there are no further launch-capture relationship between CLKC→CLKB within 0-6ns, the worst-case timing is 1ns.

Therefore, for satisfying setup time –
→ (Delay due to combo logic-1) ≤ {(worst effective clock period) – (setup time of FF-1) – (Input delay)}
→ Implies, (delay due to combo logic-1) ≤ {(1ns) – (0.1ns) – (0.55ns)}
→ Thus, maximum possible delay that can be introduced by the combo logic-1 is 0.35ns.

Constraining the output port

On our output port Output1, we have two different capturing clocks.

Here again we create the clock for CLKC of 2ns and we then create two virtual clocks, CLKE of 1ns period (corresponding to 1 GHz) and CLKD with a period corresponding to 750 MHz –

create_clock -period 2 [get_ports CLKC]
create_clock -period 1 -name CLKE
create_clock -period [expr {1000/750.0}] -name CLKD

Note: While using expr command, it is important for one of the two numbers to be a real number so that the resulting number is also a real number.

Now we specify the output delay relative to the virtual clock CLKD and we apply that to our output port Output1 –

set_output_delay -max 0.15 -clock CLKD [get_ports Output1]

And then we follow up with another output delay relative to the virtual clock CLKE on the same output port –

set_output_delay -max 0.52 -clock CLKE -add_delay [get_ports Output1]

Note: We are using add_delay option in the second constraint since we are applying the constraint to an already constrained port; this ensures the second constraint doesn’t overwrite the first one.

We want the synthesis tool to consider both the paths and optimize the output path through combo logic-3 for the worst-case scenario of either of the two capturing paths. Assuming the setup time of both the flops FF-4 and FF-5 as 1ns and the combinational delay of combo logic-7 and combo logic-8 as 0.1ns and 0.47ns respectively, let’s see how that calculation is done.

Here again the first thing the tool does is to calculate the base period. The least common multiple of the three clock periods is 4ns. If you look at the waveform shown in Figure 4, at 4ns all the clock edges line up and starts rising again.

Figure 4: Worst effective clock period for output paths in the base period

Since there are two launch-capture paths from CLKC→CLKD and CLKC→CLKE, the tool will consider both paths and pick the worst timing relationship of all the edges between both the launch-capture path relationship. As shown in the waveform, there are four pairs of launch-capture relationship between 0-4ns and the worst effective clock period between CLKC→CLKD launch-capture path is 0.67ns and the worst effective clock period between CLKC→CLKE launch-capture path is 1ns.

Now let us calculate the critical path between the two launch-capture paths –

For CLKC→CLKD path:
→ (Delay due to combo logic-3) ≤ {(worst effective clock period) – (Output delay)}
→ Implies, (delay due to combo logic-3) ≤ {(0.67ns) – (0.2ns)}
→ Thus, maximum possible delay that can be introduced by the combo logic-3 for CLKC→CLKD path is 0.47ns.

For CLKC→CLKE path:
→ (Delay due to combo logic-3) ≤ {(worst effective clock period) – (Output delay)}
→ Implies, (delay due to combo logic-3) ≤ {(1ns) – (0.57ns)}
→ Thus, maximum possible delay that can be introduced by the combo logic-3 for CLKC→CLKE path is 0.43ns.

Considering the worst-case scenario (CLKC→CLKE path), the tool will try to optimize the combo logic-3 such that the combinational delay due to it is less than equal to 0.43ns.