# Scan Clocking Architecture

The clocking architecture of a design needs to be modified to support ‘Scan’ operation. In this article we will take an example of a very generic functional clocking architecture as shown in Figure 1 and modify it. Figure 1: An example of a typical clocking architecture (without considering scan testing requirement)

The given scenario –

As shown in Figure 1, there is a PLL which is generating three different clocks (of frequency 500 MHz, 400 MHz and 100 MHz).  The cloud like structures in the figure indicates different clock domains (having the logic we want to test).

There are two dividers –
1.  DIV (2) – which divides the input clock by 2. So the frequency of the clock at the output of divider is 200 MHz.
2.  DIV (1 or 4) – which either divides the input clock by 4 or bypasses it without any division, depending upon the functional requirement. So the frequency of clock at the output of divider is either 500 MHz or 125 MHz.

The dividers have functional control that determines the division ratio of the divider. The divider ‘DIV (2)’ always divides the input clock by a constant value of 2; typically in such dividers the functional control, excluding the reset to divider is likely to be tied to a constant value in the design. But the divider ‘DIV (1 or 4)’ can either divide the input by 4 or bypass it; typically the functional control of such dividers are controlled by a FSM (or any other controlling logic).

There is also a clock mux, which has a functional control that selects which clock it should propagate at its output. The frequency of the clock at the clock mux output can be either 200 MHz (from the divider) or 100 MHz (from the PLL). Like the dividers, the functional control in a clock mux is typically controlled by a FSM (or any other controlling logic).

Modifications required –

Now let us go through the modifications needed in clocking architecture for making the design ‘Scan’ friendly –

In stuck-at testing the frequency of the clock domain we will be testing doesn’t matter; but in at-speed testing, we should be testing the clock domain at the maximum frequency it supports because of the reason discussed here. The frequency shown in red inside the clock domains (cloud like structures) in Figure 4, indicates the maximum clock frequency of that clock domain.

1.  Since we have two clock dividers and one clock mux in our design, we have to ensure the clock with the highest frequency is propagated at the output of dividers and clock mux for at-speed testing at correct frequency.

1.1.  Clock mux – Maximum possible frequency at the output is 200 MHz. Since the FSM controlling the select pin of clock mux will be part of scan chains, it will toggle during testing. Hence the clock at the output of the clock mux becomes unpredictable and can be any one of its input at any instance. To prevent this, we need to add a simple mux as shown in Figure 4, which will mask the functional control in scan mode (Test Mode = 1), to select the clock with highest frequency (in this case the 200 MHz clock).

1.2.  ‘DIV (2)’ – The 200 MHz clock at the output of clock mux is coming from the clock divider ‘DIV (2)’, thus ‘DIV (2)’ should function as a divider throughout the scan mode, so that we will get the required 200 MHz clock. If we scan the divider, the logic responsible for dividing the clock will become part of scan chain and will toggle during scan mode, resulting in clock of unpredictable frequency at the output of divider; so we should not scan this divider. Also we have to mask the reset or any other functional control that it likely to affect the functionality of the divider as shown in Figure 2. Figure 2: Diagram showing the the modifications required for divider DIV(2)

1.3.  ‘DIV (1 or 4)’ – We need the undivided clock of 500 MHz (fastest clock), thus we need to mask the functional control to select the undivided clock in scan mode, as shown in Figure 3. Since we are bypassing the divider, we can scan this divider as it will not affect the divider output. Figure 3: Diagram showing the modifications required for divider DIV(1 or 4)

2.  Then we need to modify the clocking architecture to add an On-chip Clock Controller(OCC) for every clock domain, as shown in Figure 4. We have six clock domains, thus six OCCs. As discussed here, the OCC controls the clock operation required for testing a circuit.

Although the scan clocking architecture (shown in Figure 4) can be further optimized for this particular example, but this is a much cleaner and generic representation to illustrate how we need to define a Scan friendly clocking architecture.

Note: Ensure all the clock(s) to the input of a divider or a clock mux should be free running, meaning it should not be coming from an OCC. Figure 4: Modification required in the clocking architecture shown in Figure 1, to support ‘Scan’ operation