Isolation cells and Level Shifter cells

Isolation Cells

Isolation cells are additional cells inserted by the synthesis tools for isolating the buses/wires crossing from power-gated domain of a circuit to its always-on domain. The isolation list is a list which consists of all the buses/wires that needs isolation cells. In the isolation list we specify the clamping value of the nets as logic 0 or logic 1 and accordingly the synthesis tool will insert isolation cells.

Why do we need it?

Figure 1: A simple circuit having a switchable (or gated) power domain

Consider a very simple circuit as shown in Figure 1, where G1 and G2 are in power gated domain. Now in low power mode when the power to the power gated domain is cut off, the output of G1 and G2 becomes unknown (or ‘X’). So the logic in the always-on domain will be affected by it. To prevent corruption of always-on domain, we clamp the nets crossing the power domains to a value depending upon the design.

Here we will put the output wire from G1 and G2 in isolation list and clamp the value to logic 0 and logic 1 respectively. After synthesis the circuit will look like the one shown in Figure 2.

Figure 2: The circuit shown in Figure 1, after isolation cells are inserted

Typically when we clamp a wire to value 0, an AND gate is inserted by the synthesis tool with one of its input connected to an isolation enable signal from the Power Management Unit (PMU) sitting inside your design, as shown in the diagram. Similarly, when we clamp a wire to value 1, an OR gate is inserted by the synthesis tool with one of its input connected to the inverted version of the isolation enable signal. These tool inserted AND and OR gates are known as isolation cells.

Since the PMU manages all the power gating inside a design, it enables the isolation enable signal before power gating to make sure there is no ‘X’ value propagated to aon-domain after power is cut off. In the diagram above, isol_pgd_en is the isolation enable signal and is an active low signal.

Level Shifter Cells

Level Shifters (LS) are special standard cells used in Multi Voltage designs to covert one voltage level to another. As Multi Voltage designs have more than one voltage domain, level shifters are used for all the signals crossing from one voltage domain to another voltage domain. Like isolation cells, level shifters are inserted by the synthesis tool.

Low to High Level Shifters

Low to High LS are used for signals crossing from a lower voltage domain to higher voltage domain.
It basically amplifies the source signal so that it can be interpreted properly in the destination domain. Suppose a 0.7V signal is crossing from 0.7V voltage domain to 1.0V voltage domain. Now in the lower voltage domain it corresponds to logic-1 but in higher voltage domain it is neither logic-1 nor logic-0, so the signal becomes unknown (or ‘X’) in the absence of Low to High LS.

High to Low Level Shifters

High to Low LS are used for signals crossing from higher voltage domain to lower voltage domain.
It basically attenuates the source signal. Although putting a LS for signals crossing from higher voltage domain to lower voltage domain is optional as signals will be interpreted properly in destination domain, but typically we put a LS to avoid stress on the transistors of lower voltage domain due to high voltage of the source signal.

Bi-directional Level Shifters

When dynamic voltage scaling or dynamic voltage and frequency scaling is used the voltage relation between the source and destination might change over time of operation. In that case we need level shifter which is capable of shifting both low to high voltage signals and high to low voltage signals.

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