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VLSI Tutorials

  • Power
    • Power Dissipation
    • Power Management Techniques
    • Isolation cells and Level Shifter cells
    • Retention cells
    • UPF command syntax
    • UPF
  • DFT
    • DFT, Scan and ATPG
    • On-chip Clock Controller
    • Scan Clocking Architecture
    • LFSR and Ring Generator
    • Logic Built In Self Test (LBIST)
    • Response Analyzer
    • Test Compression
  • STA
    • Synthesis Timing Constraints
      • Constraining timing paths in Synthesis – Part 1
      • Constraining timing paths in Synthesis – Part 2
      • Constraining Multiple Synchronous Clock Design in Synthesis
      • Constraining Generated Clocks and Asynchronous Clocks in Synthesis
      • Constraining Logically Exclusive Clocks in Synthesis
      • Constraining Multi-Cycle Path in Synthesis
  • JTAG
    • JTAG Architecture
    • TAP and TAP Controller
    • Instruction Register and Instruction Decoder
    • Data Registers
    • Example showing JTAG Operation
  • Other
    • Glitch free clock mux

Other

  1. Glitch free clock mux
  2. Clock Domain Crossing (coming soon)
  3. Reset Domain Crossing (coming soon)
  4. A top view of VLSI design flow (coming soon)

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  • Power
    • Power Dissipation
    • Power Management Techniques
    • Isolation cells and Level Shifter cells
    • Retention cells
    • UPF command syntax
    • UPF
  • DFT
    • DFT, Scan and ATPG
    • On-chip Clock Controller
    • Scan Clocking Architecture
    • LFSR and Ring Generator
    • Logic Built In Self Test (LBIST)
    • Response Analyzer
    • Test Compression
  • STA
    • Synthesis Timing Constraints
      • Constraining timing paths in Synthesis – Part 1
      • Constraining timing paths in Synthesis – Part 2
      • Constraining Multiple Synchronous Clock Design in Synthesis
      • Constraining Generated Clocks and Asynchronous Clocks in Synthesis
      • Constraining Logically Exclusive Clocks in Synthesis
      • Constraining Multi-Cycle Path in Synthesis
  • JTAG
    • JTAG Architecture
    • TAP and TAP Controller
    • Instruction Register and Instruction Decoder
    • Data Registers
    • Example showing JTAG Operation
  • Other
    • Glitch free clock mux
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